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Communications Engineering (Master of Science) >>

Reconfigurable Computing with Extended Exercises (RC-VEU)7.5 ECTS
(englische Bezeichnung: Reconfigurable Computing with Extended Exercises)
(Prüfungsordnungsmodul: Reconfigurable Computing (Lecture with Extended Exercises))

Modulverantwortliche/r: Jürgen Teich
Lehrende: Jürgen Teich

Startsemester: WS 2022/2023Dauer: 1 SemesterTurnus: jährlich (WS)
Präsenzzeit: 90 Std.Eigenstudium: 135 Std.Sprache: Englisch



Reconfigurable (adaptive) computing is a novel yet important research field investigating the capability of hardware to adapt to changing computational requirements such as emerging standards, late design changes, and even to changing processing requirements arising at run-time. Reconfigurable computing thus benefits from a) the programmability of software similar to the Von Neumann computer and b) the speed and efficiency of parallel hardware execution.
The purpose of the course reconfigurable computing is to instruct students about the possibilities and rapidly growing interest in adaptive hardware and corresponding design techniques by providing them the necessary knowledge for understanding and designing reconfigurable hardware systems and studying applications benefiting from dynamic hardware reconfiguration.
After a general introduction about benefits and application ranges of reconfigurable (adaptive) computing in contrast to general-purpose and application-specific computing, the following topics will be covered:

  • Reconfigurable computing systems: Introduction of available technology including fine grained look up table (LUT-) based reconfigurable systems such as field programmable gate arrays (FPGA) as well as newest coarse grained architectures and technology.

  • Design and implementation: Algorithms and steps (design entry, functional simulation, logic synthesis, technology mapping, place and route, bit stream generation) to implement (map) algorithms to FPGAs. The main focus lies on logic synthesis algorithms for FPGAs, in particular LUT technology mapping.

  • Temporal partitioning: techniques to reconfigure systems over time. Covered are the problems of mapping large circuits which do not fit one single device. Several temporal partitioning techniques are studied and compared.

  • Temporal placement: Techniques and algorithms to exploit the possibility of partial and dynamic (run-time) hardware reconfiguration. Here, OS-like services are needed that optimize the allocation and scheduling of modules at run-time.

  • On-line communication: Modules dynamically placed at run-time on a given device need to communicate as well as transport data off-chip. State-of-the-art techniques are introduced how modules can communicate data at run-time including bus-oriented as well as network-on-a-chip (NoC) approaches.

  • Designing reconfigurable applications on Xilinx Virtex FPGAs: In this part, the generation of partial bitstreams for components to be placed at run-time on Xilinx FPGAs is introduced and discussed including newest available tool flows.

  • Applications: This section presents applications benefiting from dynamic hardware reconfiguration. It covers the use of reconfigurable systems including rapid prototyping, reconfigurable supercomputers, reconfigurable massively parallel computers and studies important application domains such as distributed arithmetic, signal processing, network packet processing, control design, and cryptography.

Lernziele und Kompetenzen:

Learning objectives and competencies:

  • The students know to exploit run-time reconfigurable design methodologies for adaptive applications.
  • The students understand the mapping steps, and optimization algorithms.
  • The students classify different types and kinds of reconfigurable hardware technologies available today.

  • The students clarify pros and cons of reconfigurable computing technology.

  • The students summarize applications benefiting from reconfigurable computing.

  • The students apply design tools for implementation of circuits and systems-on-a-chip (SoC) on FPGAs during practical training.
  • The students perform group work in small teams during practical training.



Reconfigurable computing is an interdisciplinary field of research between computer science and electrical engineering.


Selection of this module prohibits the selection of the module "Reconfigurable Computing (RC-VU)" by the student.

Weitere Informationen:

www: https://www.cs12.tf.fau.de/lehre/lehrveranstaltungen/vorlesungen/reconfigurable-computing/

Verwendbarkeit des Moduls / Einpassung in den Musterstudienplan:

  1. Advanced Signal Processing & Communications Engineering (Master of Science)
    (Po-Vers. 2021w | TechFak | Communications Engineering (Master of Science) | Gesamtkonto | Technical Electives | Reconfigurable Computing (Lecture with Extended Exercises))
Dieses Modul ist daneben auch in den Studienfächern "Informatik (Bachelor of Arts (2 Fächer))", "Informatik (Bachelor of Science)", "Informatik (Master of Science)", "Information and Communication Technology (Master of Science)", "Informations- und Kommunikationstechnik (Master of Science)", "Mathematik (Bachelor of Science)", "Mechatronik (Bachelor of Science)", "Mechatronik (Master of Science)", "Medizintechnik (Master of Science)" verwendbar. Details


Reconfigurable Computing (Lecture with Extended Exercises) (Prüfungsnummer: 714289)
Prüfungsleistung, mündliche Prüfung, Dauer (in Minuten): 30, benotet
Anteil an der Berechnung der Modulnote: 100.0 %
weitere Erläuterungen:
Oral examination (Duration: 30 min) and successful completion of all tasks of the extended exercises (mandatory, at the workstations residing in our lab at the chair).
The oral examination determines the final grade of the module.

Erstablegung: WS 2022/2023, 1. Wdh.: SS 2023
1. Prüfer: Jürgen Teich

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