Rechnerarchitektur
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VORL; 2 SWS; Fr, 8:15 - 9:45, 07.150
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WPF INF-BA-V-RA 4-6
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Sieh, V.
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Laborübungen zu CPU-Design [LÜCPU]
UE; 2 SWS; Fr, 10:15 - 11:45, 07.150
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WPF INF-BA-V-RA 4-6
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Sieh, V.
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Übungen zu CPU-Design [ÜCPU]
UE; 2 SWS; Do, 12:15 - 13:45, 07.150
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WPF INF-BA-V-RA 4-6
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Sieh, V.
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VORL; 2 SWS; ben. Schein; Mi, 14:15 - 15:45, 07.150
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WPF INF-BA-V-RA 4-6
WF IuK-BA ab 5
WF CE-BA-TW ab 5
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Schmidt, M.
Reichenbach, M.
Fey, D.
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Übungen zu Digitaler Schaltungsentwurf mit VHDL [ÜVHDL-RA]
UE; 2 SWS; Mo, 14:15 - 15:45, 07.150
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WPF INF-BA-V-RA 4-6
WF IuK-BA ab 5
WF CE-BA-TW ab 5
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Reichenbach, M.
Schmidt, M.
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VORL; 2 SWS; Schein; Fr, 12:15 - 13:45, 07.150
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WF IuK-BA ab 5
WPF IuK-BA 1-3
WF CE-MA-INF 1-3
WF CE-BA-TW ab 5
WPF INF-BA-V-RA ab 5
PF INF-MA 1-3
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Reichenbach, M.
Fey, D.
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Laborübung zu Einführung digitaler ASIC Entwurf [LÜEDA]
UE; 2 SWS; ECTS: 2,5; Mo, 12:15 - 13:45, 02.153; ab 23.4.2012
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WF IuK-BA ab 5
WF CE-MA-INF 1-3
WF CE-BA-TW ab 5
WPF INF-BA-V-RA ab 5
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Reichenbach, M.
Pfundt, B.
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VORL; 4 SWS; ECTS: 5; Di, 8:30 - 10:00, 07.150; Fr, 10:15 - 11:45, 04.150
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WPF INF-BA-W 5-6
WPF INF-BA-W 5-6
WPF INF-BA-S 4-6
WPF INF-MA ab 1
WF CE-BA-TW 5-6
WF CE-MA-INF ab 1
WF IuK-BA 5-6
WPF IuK-MA-ES-INF 1-3
WPF IuK-MA-KN-INF 1-3
WPF IuK-MA-REA-INF 1-3
WPF IuK-MA-ÜTMK-INF 1-3
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Fey, D.
Veldema, R.
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Tafelübungen zu Einführung digitaler ASIC Entwurf [TÜEDA]
UE; Fr, 14:15 - 16:15, 02.153
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WF IuK-BA ab 5
WF CE-MA-INF 1-3
WF CE-BA-TW ab 5
WPF INF-BA-V-RA ab 5
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Reichenbach, M.
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Tutorium zur Prüfung GRa
TUT; Zeit und Raum n.V.
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Fey, D.
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UE; 2 SWS; ECTS: 2,5; Mi, 10:15 - 11:45, 04.150; nV. (in der ersten Vorlesung)
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WPF INF-BA-W 5-6
WPF INF-BA-S 5-6
WPF INF-MA ab 1
WF CE-BA-TW 5-6
WF CE-MA-INF ab 1
WF IuK-BA 5-6
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Veldema, R.
Schäfer, A.
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